2.4 GHz Low Power Bluetooth Receiver

2.4 GHz Low Power Bluetooth Receiver RWTH IAS

Reducing power consumption of tranceiver systems is a non-extingushing trend in electronics industry. However, with the steep increase in the number of portable electronic devices that include embedded wireless systems over the last years, the demand towards low power receivers is now boosted. The talk time of a cellular phone or life time of a wireless sensor is directly dictated by the current consumption of the system.

This project targets for a low power Bluetooth system. A low IF topology is applied by designing the receiver frontend part, where LNA and mixer are implemented in low current architectures. Inside the backend part a novel 1-bit Delta Sigma AD Converter is being used to achieve high resolution with little power. The Delta Sigma ADC is designed with a capacitive summation technique instead of using the traditional resistive summation approach, and thus it results in a considerable power reduction. In baseband, analog and digital processing is done on the same chip which gives the SoC architecture.

Lei Liao < >
Aytac Atac < >