Advanced RF modeling and simulation techniques for fast SoC functional verification

Advanced RF modeling and simulation techniques for fast SoC functional verification RWTH IAS

Verification is becoming a key task in today's design of complex, highly integrated circuits. More and more digital functionality enters the formerly analog-only radio frequency (RF) circuit blocks. Since the digital calibrated analog building blocks need a huge number of digital connections and programming routines, a verification of the complex interaction between all of them is inevitable. The mission of so called functional verification prior to tape-out is to provide modeling and simulation strategies, which will seamlessly embed into the whole design flow, in order to handle the complexity of the chips and to avoid the re-spins because of connectivity bugs or misinterpreted interface specifications.

This project aims at researching and developing formalized modeling methodologies based on hardware Description languages (HDLs) like Verilog-/VHDL-AMS and SystemC/-AMS, which enables test bench with switchable abstraction levels for each sub systems to ensure verification possibilities in all necessary levels. Eliminate the need of time consuming RF solution by building pin-compatible models based on the schematic database. Additionally, novel concepts that provide Virtual RF prototyping possibilities in SystemC for advanced Mixed-Signal verification of nano-scale SoCs include new digital RF concepts like RFDACs as well as charge sampling receivers.

Yifan Wang < >